1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of manufacturing the same, and particularly relates to a semiconductor device having a high breakdown voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a method of manufacturing the same.
2. Description of the Related Art
For example, semiconductor integrated circuits having charge control functions for mobile phones are usually driven at a voltage of 5-6 V (volts), and the rated voltage thereof is about 8 V. If the semiconductor integrated circuits are connected to a defective adapter, a voltage higher than the rated voltage, e.g. 12 V-18V, might be applied to internal circuits. It is therefore desirable that the internal circuits be able to operate normally without having any problems, such as heat generation and failure, even when encountering such a situation.
Display system devices such as liquid crystal display devices are also required to operate in a high voltage band of about 15 V and at high current. That is, transistors having higher breakdown voltage and operable at higher current support the recent developments of mobile phones and digital communication drives.
There are various methods of increasing the rated voltage of MOSFETs. One method is to provide a thick oxide film under a gate oxide film at the drain side, and a second drain region under the thick oxide film. This type of MOSFET having the thick oxide film made of a LOCOS (local oxidation of silicon) oxide film for element separation is called a LOCOS offset transistor.
In manufacture of such a LOCOS offset transistor, increasing the rated voltage goes against improvement of drive performance. This is because if impurity concentration of the second drain region is increased, electric field concentration in the vicinity of the gate insulation film is significantly increased, which results in reduction of the breakdown voltage between the drain and a semiconductor substrate. In addition, expansion of a depletion layer between the second drain region and the semiconductor substrate is prevented, which also results in reduction of the breakdown voltage between the drain and the semiconductor substrate. On the other hand, if the impurity concentration of the second drain region is reduced, parasitic resistance of the drain is increased, which lowers drive performance. That is, the configuration of the second drain region is a key to balance the breakdown voltage and the drive performance at higher levels.
FIG. 15 shows a first related art MOSFET (see, for example, Patent Document 1). In this MOSFET, a P+ drain region 86 of medium concentration and a P− drain region 88 of low concentration are formed between a P++ drain region 82 and a gate oxide film 84 disposed on the surface of an N-type semiconductor substrate 80. The P+ drain region 86 is formed under a thick LOCOS oxide film 90, whereas the P− drain region 88 is disposed under the gate oxide film 84.
A problem with the configuration of FIG. 15 is that the P++ drain region 82 is in direct contact with the N-type semiconductor substrate 80, which prevents expansion of a depletion layer and therefore might cause junction destruction at low voltage. Patent Document 1 also discloses a configuration in which a P− drain region is disposed under the P++ drain region 82. Even with this configuration, as the P+ drain region 86 is in direct contact with the N-type semiconductor substrate 80, the breakdown voltage cannot be sufficiently increased for the same reason.
Another problem with the MOSFET disclosed in Patent Document 1 is that because the P− drain region 88 is formed in contact with the gate oxide film 84 after the LOCOS oxide film 90 is formed, reduction of the electric field in the vicinity of a region where the P− drain region 88 is in contact with the gate oxide film 84 is prevented, which limits the expansion of the depletion layer and therefore causes gate modulation junction destruction at low drain voltage.
FIG. 16 shows a second related art MOSFET (see, for example, Patent Document 2). In this MOSFET, a thick LOCOS oxide film 90 is formed at a channel region side of a first drain region 92 of high impurity concentration, and a shallow second drain region 94 of high impurity concentration is formed directly under the LOCOS oxide film 90. Further, a deep third drain region 96 of low impurity concentration is formed to surround the second drain region 94.
A problem with this MOSFET is that because impurities for the shallow second drain region 94 are introduced directly under a region where the LOCOS oxide film 90 is to be formed before forming the LOCOS oxide film 90, the MOSFET is easily affected by ion attraction into the LOCOS oxide film 90 and ion segregation at the interface between the LOCOS oxide film 90 and a semiconductor substrate 80, which makes the drive performance susceptible to process changes.
Another problem with this MOSFET is that because the shallow second drain region 94 of high concentration is formed in the vicinity of a gate oxide film 84, the strength of the electric field between the gate and the drain is increased, which results in reduction of the breakdown voltage of the gate oxide film 84.
Moreover, because the first drain region 92 of high concentration is in direct contact with the P-type semiconductor substrate 80, expansion of a depletion layer is prevented, which causes junction destruction at low drain voltage.
<Patent Document 1> Japanese Patent Laid-Open Publication No. 6-21445
<Patent Document 2> Japanese Patent Registration No. 2668713